Electromagnetic energy detection

ABSTRACT

The invention provides apparatus and methods for detecting electromagnetic energy using an array of detectors arranged in at least one row and multiple columns. A single crystal body has multiple doped regions disposed therein. Each one of the detectors produces charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon that detector. A first charge transfer device includes an output port and multiple serially coupled charge storage cells including multiple first charge transfer regions disposed in the body parallel to the row, or rows, of detectors. Multiple second charge transfer devices include multiple second charge transfer regions disposed in the body transverse to the row, or rows, of detectors and the charge storage cells. Each one of the second charge transfer regions is adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the charge storage cells. Each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the multiple second charge transfer regions. Such an arrangement allows dual polarization detection with little or no modification of the system configuration.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of U.S. patent application Ser. No. 09/038,251, filed on Mar. 10, 1998, now U.S. Pat. No. 6,239,702.

BACKGROUND OF THE INVENTION

This invention relates generally to energy detection systems and more particularly to energy detection systems disposed on a single crystal substrate.

As is known in the art, electromagnetic energy detection systems have a wide range of application, e.g. from cameras to missile seekers. In such systems, electromagnetic energy, e.g., visible light or infrared energy, is focused by an optical system onto one, or more, electromagnetic energy detectors. These detectors are often arranged in an array which is disposed at the focal plane of the optical system. The detector produces an indication of the detected energy by, for example, producing a corresponding electrical output signal. In one focal plane array, the detectors are semiconductor devices, such as HgCdTe or InSb, formed in different isolated regions of an upper surface of a single crystal semiconductor body. Thus, in response to light impinging upon the detector, charge is produced in the corresponding isolated region of the semiconductor body having the detector.

In one system, a read-out electronics (“ROE”), formed as an integrated circuit in a second semiconductor substrate, typically silicon, is mounted to a back surface of the first-mentioned substrate. The charge produced in the first-mentioned substrate passes to different isolated regions of the second-mentioned substrate through electrical contacts disposed therebetween. The read-out electronics provides clock signals to regulate the propagation of charge in the second-mentioned substrate to output signal processing circuitry. In order to transfer the charge produced in the first-mentioned substrate to the second substrate, a wire or other metal contacts are connected to ohmic contact diffusion regions in the semiconductor bodies to provide electrical contact. The ohmic contact regions result in the generation of generation-recombination (GR) noise. While this technique may be acceptable for some wavelengths of energy, the GR noise produced may create, in some applications, an unacceptably low signal to noise ratio (SNR) for some combinations of wavelength and substrate.

The use of a single silicon substrate for both the detectors and the read-out electronics has been suggested. However, with a silicon substrate, near infrared energy above about 8,000 Å passes readily through the substrate without generating sufficient charge for system SNR requirements. One technique has been presented in two articles, one entitled “Active-Pixel Image Sensor Integrated With Readout Circuits,” by Robert Nixon, Eric Fossum, and Sabrina Kemeny and the other entitled “CMOS Active-Pixel Image Sensor Containing Pinned Photodiodes,” by Eric R. Fossum both published in NASA Tech Briefs, October, 1996, from NASA's Jet Propulsion Laboratory in Pasadena, Calif. In the articles, the authors describe an attempt at an image sensor including readout circuits and pinned diode detectors, for visible and ultraviolet light, on one chip. According to the second-mentioned article, however, the operation of the device has not been demonstrated.

SUMMARY OF THE INVENTION

In accordance with one feature of the invention, an electromagnetic energy detection system is provided having a plurality of detectors disposed in a single crystal body. Each one of the detectors is adapted to produce charge in a doped region disposed in the body in response to electromagnetic energy impinging upon such one of the detectors. A first charge transfer device (“CTD”) is provided having a plurality of first charge transfer regions disposed in the body and includes a plurality of serially coupled charge storage cells. A plurality of second charge transfer devices is provided for transferring the charge in a corresponding one of the doped regions to a corresponding one of the charge storage cells of the first charge transfer device.

With such an arrangement, ohmic contacts between each one of the detectors and the charge storage cells of the first charge transfer device are eliminated thereby reducing GR noise and improving the SNR performance of the detection system.

In accordance with another feature of the invention, an electromagnetic energy detection system is provided having a plurality of detectors disposed in a single crystal body. Each one of the detectors is adapted to produce charge in the body in response to electromagnetic energy impinging upon such one of the detectors. Read-out electronics is disposed on the body. The read-out electronics includes a first charge transfer device having a plurality of first charge transfer regions disposed in the body and includes a plurality of serially coupled charge storage cells. A last one of the cells is coupled to an output port. A charge coupling structure is disposed on the body to couple the charge produced by the detectors to the read-out electronics, The charge coupling structure includes a plurality of second charge transfer devices, including a plurality of second charge transfer regions, disposed in the body. Each one of the plurality of second charge transfer regions is adapted to transfer charge produced in a corresponding one of the detectors to a corresponding one of the plurality of charge storage cells. With such an arrangement, an effective electromagnetic energy detection system is provided wherein energy detectors, charge coupling structure and read-out electronics are formed on a single crystal substrate.

In a preferred embodiment of the invention, a shield is provided to reduce incident electromagnetic energy from impinging upon portions of the read-out electronics and portions of the charge coupling structure.

In accordance with still another feature of the invention, a detector is provided having a single crystal body with a doped region therein. Such detector is adapted to produce charge in the doped region in response to electromagnetic energy impinging upon such detector. A second region is disposed in the body and laterally displaced from the detector. The doped region has a doping profile selected to produce an electric field therein along a direction from the doped region toward the second region.

With such a structure, charge produced in the body is efficiently transferred from the doped region to a region displaced therefrom for processing by electronic circuitry also disposed on the body.

In a preferred embodiment, the body comprises silicon and the detector comprises a light detector.

In accordance with still another feature of the invention, apparatus is provided for reducing noise, e.g., transients, in an output of a charge transfer device formed in a first region of a single crystal body. Such apparatus includes a transient suppression circuit. The circuit includes a pair of inputs; one of the inputs being coupled to the output of the charge transfer device and the other input being coupled to a second region of the body displaced from the first region. The circuit includes a differencing arrangement for subtracting signals at the pair of inputs to reduce noise components on at least one of such signals.

With such an arrangement, noise generated in the body is present at the output of the charge transfer device, along with a desired signal, and is also present in the second region of the body. Therefore, substantially the same noise is present at both of the inputs of the transient suppression circuit. The differencing arrangement combines the two signals at the two inputs to thereby cancel, or reduce, the noise present at the output of the charge transfer device thereby yielding the desired signal with a reduced noise component.

In accordance with another feature of the invention, an electromagnetic energy detection system is provided having a single crystal body. A detector is disposed in a first region the body. The detector produces charge in the body in response to electromagnetic energy impinging upon such detector. At least a portion of the produced charge passes through a second region of the body to an output port. A charge detector, disposed in the body, is coupled to the output port and produces a charge detector output signal indicative of detected charge. A sensor having an input port coupled to the body in a third region of the body produces a sensor output signal indicative of signals induced on the input port.

In a preferred embodiment, a differencing device is provided. The charge detector, the sensor, and the differencing device are arranged to provide an output indicative of detected energy. A first transfer device is provided to couple the produced charge from the detector to the output port. The charge detector is adapted to receive charges from the output port and to provide a charge detector signal. The sensor has an input coupled to the body in the third region of the body and is adapted to provide a sensor output signal. The differencing device is adapted to receive the charge detector signal and the sensor output signal to provide a difference output signal indicative of a difference of the sensor output signal and the charge detector signal. With such an arrangement, common mode noise is reduced, improving the dynamic range of the signal processing channel receiving the detected energy.

The invention provides numerous other advantages. For example, the invention provides a fully integrated system for real time image acquisition. Integrating multiphase clock generators, detectors, and read-out electronics on a single chip avoids a complex interface of wires and external electronics, allowing for simple and efficient system performance. Doping configurations and detector selection allow ±5V power supplies to operate the charge transfer devices, e.g. Buried Channel Charge Coupled Devices (BCCDs), and “pinned” diode detectors. By using buried channel charge coupled devices, extraneous wires are eliminated, reducing GR noise and improving SNR, and reducing stray inductance and capacitance and electromagnetic interference. The invention is easily adapted for multispectral (color) imaging to achieve multimegapixel color imaging, small package size, and low price, which is useful for applications such as scanning digital cameras. The invention is also suited for laser tomography.

BRIEF DESCRIPTION OF THE DRAWING

Other features and advantages of the invention, as well as the invention itself, will become more readily apparent when taken together with the following detailed description and the accompanying drawings, in which:

FIG. 1 is a diagrammatical layout of an electromagnetic energy detection system;

FIG. 2 is an enlarged view of a portion of the system of FIG. 1;

FIG. 3 is a simplified cross-sectional view of an electromagnetic detector and charge coupling structure, such cross-section being taken along line 3—3 in FIG. 2;

FIG. 4 is a plot of voltage as a function of vertical distance in the detector of FIG. 3;

FIG. 5A is cross-sectional view of an electromagnetic detector and charge coupling structure;

FIGS. 5B and 5C are plots of voltage gradients in the electromagnetic detector and charge coupling structure of FIG. 5A;

FIG. 6 is a cross-sectional view of charge transfer device read-out electronics, such cross-section being taken along the line 6—6 in FIG. 2;

FIG. 7A is a partially cross-sectional view and a partially schematic diagram of an output portion of the system of FIG. 1;

FIG. 7B is a voltage diagram of an output signal of a buffer amplifier of FIG. 7A;

FIG. 8 is an operational flow diagram of the system of FIG. 1;

FIG. 9 is a diagrammatical side view of a filter arrangement for the system of FIG. 1;

FIG. 10 is a side view of a gimbal scanning arrangement for the system of FIG. 1;

FIG. 11 is a side view of an aperture scanning arrangement for the system of FIG. 1; and

FIG. 12 is a schematic diagram of a Brewer detector arrangement.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

General

In FIG. 1, an electromagnetic energy detection system 10 is shown. The system 10 is formed on a single crystal semiconductor chip, or body 12, here having a p-type conductive silicon substrate 13. The detection system 10 is arranged in four similarly-structured quadrants 14 a-14 d. Each one of the quadrants 14 a-14 d includes an array of detectors 16 ₁-16 _(n), a charge transfer device read-out electronics (CTD ROE) 18 coupled to a read-out electronics driver section 20, a charge coupling structure 22 coupled to a charge coupling structure driver section 24, and a transient signal suppression circuit 26, all arranged as shown. The system 10 further includes a control circuit 27 disposed at one end of the body 12 as shown. The CTD ROE 18 and portions of the charge coupling structure 22, as described below, are charge transfer devices, preferably buried channel charge coupled devices. Connections from the control circuit 27 to the driver sections 20 and 24, and from the driver sections 20 and 24 to the charge transfer device read-out electronics 18 and to the charge coupling structures 22, respectively, are bus connections. The body 12 includes a plurality of interface pins 15. An n-type guardring 93 is implanted (e.g., doped with Phosphorous) in the substrate 13 surrounding the detectors 16, charge coupling structures 22, charge transfer device read-out electronics 18, and transient suppression circuits 26, and is biased, e.g., to 5V. The guardring 93 transfers spurious noise charges away from the detectors 16 ₁-16 _(n) and the charge transfer device read-out electronics 18 to help preserve the SNR of the system 10.

Referring now also to FIG. 2, an exemplary one of the quadrants 14 a-14 d, here quadrant 14 d is shown. The quadrant 14 d includes a linear array 17 of the detectors 161 ₁-16 _(n). Each one of the detectors 16 ₁-16 _(n) is here a pinned diode detector to be described in detail in connection with FIG. 3. Suffice it to say here, however, that each one of the detectors 16 ₁-16 _(n) produces charge in body 12 in response to electromagnetic energy impinging upon such one of the detectors 16 ₁-16 _(n). The charge transfer device read-out electronics 18 includes a plurality of serially coupled charge storage cells 28 ₁-28 _(n). Each one of charge storage cells 28 ₁-28 _(n) corresponds to one of the detectors 16 ₁-16 _(n). The charge coupling structure 22 includes a plurality of charge transfer devices 30 ₁-30 _(n) each one being between a corresponding one of the detectors 16 ₁-16 _(n) and a corresponding one of the charge storage cells 28 ₁-28 _(n).

The charge transfer devices 30 ₁-30 _(n) are controlled by signals received from the charge coupling structure driver section 24 for transferring the charge in a corresponding one of the of the detectors 16 ₁-16 _(n) through the substrate 13 of a corresponding one of the charge storage cells 28 ₁-28 _(n) of the charge transfer device read-out electronics 18 as indicated by directional lines 31 ₁-31 _(n).

The charge transfer device read-out electronics 18 is controlled by signals received from the read-out electronics driver section 20 for transferring charge received from the charge transfer devices 30 ₁-30 _(n) through the substrate 13 to an output port 32 as indicated by directional line 34. More particularly, the read-out charge transfer device 18 includes the output port 32 which is fed by the last one of the serially coupled charge storage cells 28 ₁ 28 _(n), i.e., by 28 _(n). The output port 32 is coupled to the transient signal suppression circuit 26. It is noted that the read-out electronics charge transfer device 18 is disposed parallel to the rows of detectors 16 ₁-16 _(n). Each one of the charge transfer devices 30 ₁-30 _(n) is disposed in the body 12 transverse to the linear array 17 of detectors 16 ₁-16 _(n) and the charge storage cells 28 ₁-28 _(n).

Detectors 16 ₁-16 _(n)

Referring now to FIG. 3, an exemplary one of the detectors 16 ₁-16 _(n), here 16 ₁, along with the corresponding charge transfer device 30 ₁ of the charge coupling structure 22, and the corresponding charge storage cell 28 ₁ of the read-out electronics charge transfer device 18, are shown. The detector 16 ₁ is bordered on one end by a silicon dioxide insulator 42 and on the other end by the charge storage cell 28 ₁ of the charge transfer device read-out electronics 18. Such detector 16 ₁ includes: a p-type anode 44 (e.g., doped with Boron), a cathode 45 provided by an undoped portion 47 of the substrate 13 (i.e., not altered from the original doping of the substrate 13), an n-type modulating layer 48, and an n-type Buried Channel Charge Coupled Device (BCCD) layer 50, all arranged as shown. The modulating layer 48 and the BCCD layer 50 are used to transfer charge produced by the detector 16 ₁ through the substrate 13 to the corresponding charge storage cell 28 ₁ of the charge transfer device read-out electronics 18 as indicated by directional arrow 31 ₁. The cathode 45 is biased to the same potential as the anode 44, making the detector 16 ₁ a “pinned” diode (i.e., the anode 44 and cathode 45 are pinned to the same potential). The detector 16 ₁ is low lag pinned diode with potentials of the anode 44 and the substrate 13 set to −5V.

To help collect produced charge, the anode 44, cathode 45, modulating layer 48, and BCCD layer 50 are arranged to have a doping profile to produce a voltage distribution along a vertical axis x of the detector 16 ₁. Referring also to FIG. 4, the voltage at a surface 54 of the anode 44 along axis x is biased to a voltage V_(B). The voltage level increases from top to bottom in FIG. 4. The anode 44 modulating layer 48, BCCD layer 50, and substrate 13 have doping concentrations that produce voltage levels that, when moving away from the surface 54 along axis x into the detector 16 ₁, initially increase, reaching a maximum of V_(m) volts at a distance x_(m) into the detector 16 ₁, and then gradually return to V_(B), approximately reaching V_(B) at distance x_(B) into the detector 16 ₁. The thicknesses and doping concentrations are configured to produce a maximum voltage at a desired level and at a desired distance into the detector 16 ₁ in order to collect sufficient charge produced in the detector 16 ₁ to achieve an acceptable SNR. Typically, the anode 44 and modulating layer 48 are implanted less than several microns, but are capable of influencing the voltage levels further into the detector 16 ₁.

For example, the anode 44 can implanted to a depth of about 0.2 μm with an average carrier concentration of 10²⁰/cm², and the modulating layer 48 implanted to an effective depth of 0.4 μm, and V_(B) set to −5V. With appropriate doping concentrations, V_(m) can be varied as desired, with X_(m) being about 0.7 μm, and x_(B) being about 4.5 μm.

To further help collect produced charge, the anode 44 cathode 45, modulating layer 48, and BCCD layer 50 are arranged to produce a voltage distribution along a horizontal axis y of the detector 16 ₁. The modulating layer 48 lies under a portion of the anode 44 close to the charge transfer device 30 ₁. The BCCD layer 50 lies under the entire modulating layer 48, plus an additional portion of the anode 44 but does not reach the insulator 42. The detector is thus asymmetrical about a centerline 149 of the detector 16 ₁. Due to this asymmetrical arrangement and the doping of the layers along axis y (i.e., when moving along axis y from y₀ toward the charge transfer device 30 ₁), the voltage monotonically varies as a function of distance y, as will be described more fully in connection with FIGS. 5A-5C.

The voltage distributions produced by the layers produce electric fields in the detector 16 ₁ help collect charges produced in the detector 16 ₁. When electromagnetic energy, e.g., light or infrared energy as indicated by arrow 51, impinges upon the detector 16 ₁, charges, e.g., charges 52 a-52 c, are produced in the detector 16 ₁. The voltage distributions discussed above produce electromagnetic fields, e.g., as indicated by vectors {overscore (E)}₁, {overscore (E)}₂, and {overscore (E)}₃, that urge the produced charges 52 a-52 c toward the potential minimum x_(m) (see FIG. 4) and toward the charge transfer device 30 ₁, as indicated by arrows 55 a-55 c. Thus, if energy with a wavelength, e.g., 8,100 Å, at which the silicon substrate 13 is substantially transparent (i.e., few charges are produced in the substrate 13 near the surface 54) is impinged upon the detector 16 ₁, then the voltage distributions improve the collection of produced charges from within the substrate 13 and urge them toward the charge transfer device 30 ₁, as further illustrated in FIG. 5A-5C and described below. For example, Schottky-barrier-diode detectors, e.g., PtSi detectors, can be used to detect Yttrium-Aluminum-Garnet (YAG) laser radiation. Frequency response of PtSi detectors reaches into the megahertz region.

Charge Coupling Structure

Referring to FIG. 3, an exemplary one of the charge transfer devices 30 ₁-30 _(n), here 30 ₁, is shown. Such charge transfer device 30 ₁ includes: two gates 56 and 60, coupled to the charge coupling structure driver section 24 by lines 62 and 66 respectively, an oxide layer 68, a portion of the BCCD layer 50, and more of the undoped portion 47 of the substrate 13 . The gates 56 and 60 overlay the oxide layer 68, such oxide layer 68 being formed on the surface 54 of the substrate 13 . Beneath the oxide layer 68 is another portion of the BCCD layer 50, which overlays the undoped portion 47 of the substrate 13.

Charge transfer regions 70 and 74, are disposed beneath each of the gates 56 and 60, respectively, near to, but beneath, the surface 54. The oxide layer 68, BCCD layer 50, and substrate 13 are configured such that a “potential well” that collects charges will form in one of the charge transfer regions 70 or 74 by applying an appropriate bias potential on a corresponding one of the gates 56 or 60. Square wave clock signals swinging between two bias voltage levels VD_(low) and VD_(low) are supplied to gates 56 and 60 by one of the charge coupling structure driver sections 24 (using, e.g., CMOS inverter drivers) through lines 62 and 66, respectively. Coulombic forces produced by the clock signals supplied to gates 56 and 60 will dominate electron propagation in the charge transfer regions 70 and 74 if the gates have widths W₁ less than about 10 μm. With widths W₁ above about 10 μm, diffusion dominates the electron propagation. Because electron propagation by diffusion is much slower than when coulombic forces dominate, the gates preferably have widths W₁ less than about 10 μm.

The detectors 16 ₁-16 _(n), charge transfer devices 30 ₁-30 _(n), and charge transfer device read-out electronics 18, are configured to facilitate charge transfer from the detectors 16 ₁-16 _(n), to the charge storage cells 28 ₁-28 _(n) and to isolate the charge detectors 16 ₁-16 _(n) from the charge storage cells 28 ₁-28 _(n). The detector 16 ₁ and the charge transfer device 30 ₁ are disposed such that charges produced and collected in the detector 16 ₁ will be attracted to the potential well in charge transfer region 70 formed due to an appropriate bias on gate 56 . The number of gates in the charge transfer device 16 ₁ and their widths W₁ are selected, and the detector 16 ₁ the charge transfer device 30 ₁, and the charge transfer device read-out electronics 18 are disposed, such that the charge storage cell 28 ₁ is substantially isolated from the energy impinging on the detector 16 ₁. The charge transfer device 30 ₁ and the charge storage cell 28 ₁ are also disposed such that charges collected in the potential well in region 74 can be transferred to a potential well in a charge transfer region 76 a ₁ in the charge storage cell 28 ₁.

FIG. 5A shows a preferred arrangement for the detector 16 ₁, the charge transfer device 30 ₁, and the charge storage cell 28 ₁ shown in FIG. 3. As shown in FIG. 5A, the modulating layer 48 of the detector has four regions 48 a, 48 b, 48 c, and 48 d. Region 48 a is less heavily doped n-type than region 48 b, which is less heavily doped n-type than region 48 c, which is less heavily doped n-type than region 48 d. The doping of the regions 48 a, 48 b, 48 c and 48 d creates a monotonic variance in the potential in these regions in the y direction (i.e., from the detector 16 ₁ toward the charge storage cell 28 ₁). The charge transfer device 30 ₁ includes three gate regions 200 ₁, 200 ₂, and 200 ₃, each region having two gates 202 and 203. For example, gate region 200 ₁ has gates 202 ₁ and 203 ₁ coupled to the charge coupling structure driver section 24 through a conductor 204 ₁ and gate region 200 ₂ has gates 202 ₂ and 203 ₂ coupled to the charge coupling structure driver section 24 through a conductor 204 ₂. Doped regions 206 ₁ and 208 ₁ are disposed beneath gate 203 ₁ and doped regions 206 ₂ and 208 ₂ are disposed beneath gate 203 ₂. Regions 206 are more heavily doped n-type than the substrate 13, but less heavily doped n-type than regions 208. Regions 206 and 208 have widths W₂₀₆ and W₂₀₈ that are less than about 10 μm. The doping of the regions 206 and 208 creates a monotonic variance in the potential in these regions in the y direction (i.e., from the detector 16 ₁ toward the charge storage cell 28 ₁).

The BCCD layer 50 and the doped regions 48 a, 48 b, 48 c, 48 d, 206 and 208 are formed by one or more of up to five implants. Each of the five implants are formed by implanting, e.g., Phosphorous or Arsenic, to form an n-type implant region having a selected average concentration in a selected implant depth (x), examples of which are shown in TABLE 1. The values shown in TABLE 1 are the parameters of each implant independent of any other implant.

TABLE 1 Average Concentrations Depth (x) Implant in Carriers/cm² in μm 1   5 × 10¹¹ 1.0 2   2 × 10¹¹ 0.3 3   5 × 10¹¹ 0.3 4 2.5 × 10¹² 0.4 5 5.5 × 10¹² 0.4

The BCCD layer 50 is formed by implant 1. Region 48 a is a combination of implants 1 and 2. Region 48 b is a combination of implants 1, 2 and 3. Region 48 c is a combination of implants 1, 2, 3 and 4. Region 48 d is a combination of implants 1, 2, 3, 4 and 5. The implants can be formed in any order to yield the described combinations.

FIGS. 5B and 5C show how the potentials vary under the detector 16 ₁, and the gate regions 200 ₁ and 200 ₂ at a depth x of about 0.5-0.7 μm (FIG. 4) under two bias conditions for the exemplary doping configuration of the regions 48 a, 48 b, 48 c, 48 d, 206 and 208 described above. FIG. 5B shows that when the charge coupling structure driver section applies zero volts on conductor 204 ₁ and −5 volts on conductor 204 ₂, the potential along axis y monotonically increases in regions 220, 221, 222, 223, 224, 225 and 226, and decreases between regions 226 and 227, producing a potential gradient that collects (i.e., integrates) charges 209 produced in the detector 16 ₁ under the doped region 208 ₁. FIG. 5C shows that when the charge coupling structure driver section 24 applies −5 volts to the conductor 204 ₁ and zero volts to conductor 204 ₂, the potential along axis y monotonically increases in regions 220, 221, 222 and 223, decreases between regions 223 and 224, and monotonically increases in regions 224, 225, 226, 227, 228 and 229, causing the charges 209 previously collected under region 208 ₁ to transfer and be collected under region 208 ₂. A gate 210 is coupled to the charge coupling driver section 24 by a conductor 212, and regulates the transfer of charge collected under region 208 ₃ to the charge storage cell 28 ₁. The dopings are configured to produce potential gradients to guard against charges flowing in a direction from the charge storage cell 28 ₁ toward the detector 16 ₁.

Charge Transfer Device Read-Out Electronics

FIG. 6 shows two exemplary ones of the charge storage cells 28 ₁-28 _(n), here cells 28 ₁ and 28 ₂. The charge storage cells 28 ₁ and 28 ₂ include: six gates 78 a ₁ -f ₁ and 78 a ₂ -f ₂, respectively, coupled to the read-out electronics driver section 20 through line networks 80 ₁, 80 ₂, 82 ₁, and 82 ₂; a portion of the BCCD layer 50; and a portion of the undoped portion 47 of the substrate 13. As shown, the charge storage cells 28 ₁ and 28 ₂ are two-phase cells, one phase driving gates 78 a ₁-78 c ₁ and 78 a ₂-78 c ₂ and another phase driving gates 78 d ₁-78 f ₁ and 78 d ₂-78 f ₂. As shown in FIG. 6, the charge transfer device read-out electronics 18 is a two-phase buried channel charge coupled device.

The gates 78 a ₁ -f ₁ and 78 a ₂ -f ₂ are disposed above a portion of oxide layer 68. Beneath the oxide layer 68 is a portion of BCCD layer 50 that overlays a portion of undoped portion 47 of the substrate 13 . Voltage profiles in the charge storage cells 28 ₁-28 ₂ beneath gates 78 a ₁, 78 d ₁, 78 a ₂, and 78 d ₂ are similar to that shown in FIG. 4, except that the voltage at a surface 84 is higher than V_(B) because the surface 84 is not pinned to the same voltage as the substrate 13 . Also, under gates 78 b ₁, 78 e ₁, 78 b ₂, and 78 e ₂ are gate doped regions 88 b ₁, 88 e ₁, 88 b ₂ and 88 e ₂, and under gates 78 c ₁, 78 f ₁, 78 c ₂, and 78 f ₂ are gate doped regions 88 c ₁, 88 f ₁, 88 c ₂, and 88 f ₂. The gate doped regions 88 c ₁, 88 f ₁, 88 c ₂, and 88 f ₂ are more heavily doped n-type than gate doped regions 88 b ₁, 88 e ₁, 88 b ₂, and 88 e ₂, which are more heavily doped n-type than BCCD layer 50. For example, the gate doped regions 88 b are formed using a combination of implants 1 and 2 (TABLE 1), and the gate doped regions 88 c are formed using a combination of implants 1, 2 and 3 (TABLE 1). This doping profile is configured such that magnitudes of the potential wells in charge transfer regions 76 a ₁ -f ₁ and 76 a ₂ -f ₂ will vary monotonically along axis z (i.e., in a direction from charge storage cell 28 ₁ to charge storage cell 28 _(n)) when appropriate bias potentials are applied to the gates 78 a ₁ -f ₁ and 78 a ₂ -f ₂. Thus, charge is collected in the potential wells in charge transfer regions 76 f ₁ and 76 f ₂ under one bias condition, and in charge transfer regions 76 c ₁ and 76 c ₂ in another bias condition.

The gates 78 a ₁ -c ₁ and 78 a ₂ -c ₂ are coupled through line networks 80 ₁ and 82 ₁ to read-out electronics drivers 92 a ₁ and 92 a ₂ respectively, and the gates 78 d ₁ -f ₁ and 78 d ₂ -f ₂ are coupled through similar line networks 80 ₂ and 82 ₂, to read-out electronics drivers 92 b ₁ and 92 b ₂ respectively. The read-out electronics drivers 92 a ₁ -b ₁-92 a _(n) -b _(n) are CMOS inverter drivers, with sources of p-channel drivers bussed in common and sources of n-channel drivers bussed in common, and are disposed in the read-out electronics driver section 20. The read-out electronics drivers 92 a ₁ -b ₁ and 92 a ₂ -b ₂ supply phase clocks (i.e., a square wave swinging between two bias voltages HD_(low) and HD_(high) provided to the system 10) to the gates 78 a ₁ -f ₁-78 a _(n) -f ₁ and, as diagrammatically shown in FIG. 6, are distributed over the body 12 in the read-out electronics driver section 20 to, among other things, help dissipate heat.

The gates 78 a ₁ -f ₁-78 a _(n) -f _(n) are dimensioned and disposed to facilitate charge transfer as indicated by directional line 34. As with the gates 56 and 60 of the charge transfer devices 30 ₁-30 _(n), the gates 78 a ₁ -f ₁-78 a _(n) -f _(n) preferably have widths W₂ of less than about 10 μm to help ensure that electron propagation in transfer regions 76 a ₁ -f ₁-76 a _(n) -f _(n) occurs due to coulombic forces and not diffusion. Thus, the configuration shown in FIG. 6 works well with charge storage cell widths W_(c) up to about 60 μm of gate width plus some distance for the spaces between gates. The charge storage cells 28 ₁ and 28 ₂ are disposed such that charges collected in a potential well in charge transfer region 76 f ₁ in charge storage cell 28 ₁ can be transferred to a potential well in charge transfer region 76 a ₂ in charge storage cell 28 ₂. The dopings of the charge storage cells 28 are configured to produce potential gradients to guard against charges flowing in a direction opposite directional line 34.

Transient Suppression Circuit

As shown in FIG. 7A, an output portion 94 of each of the quadrants 14 a-14 d, here quadrant 14 d, includes a transient suppression circuit 26 having an input port 100 coupled to the output port 32 of a buffer stage 126 of the charge transfer device read-out electronics 18, and having an input port 102 coupled to a region 106 of the substrate 13 in a transient coupling region 300. An output port region 104 of the buffer stage 126 is coupled to the last charge storage cell 28 _(n), and region 106 is displaced from, but in close proximity to, region 104.

More particularly, buffer stage 126 includes an output gate 130 and a reset transistor 137. The output gate 130 overlays a portion of the oxide layer 68. Layer 68 overlays a portion of the BCCD layer 50 which overlays more of the undoped portion 47 of the substrate 13. The output gate 130 is biased by a constant voltage V_(d) and is disposed proximate to the gate 78 f _(n) of the last charge storage cell 28 _(n). Charges are transferred between the charge transfer region 76 f _(n) in the charge storage cell 28 _(n) to a charge transfer region 128 under the output gate 130 as indicated by directional line 34. As further indicated by directional line 34, a heavily doped n-type diffusion region 132, disposed in the output port region 104 of the substrate 13, attracts the charges from the charge transfer region 128. A line 134 (see also FIGS. 1 and 2) couples the diffusion region 132 to the output port 32 of the charge transfer device read-out electronics 18. The reset transistor 137 includes the diffusion region 132, a reset gate 133 and a diffusion region 135. The reset gate 133 is coupled to the control circuit 27 and is disposed on the surface 54 of the substrate 13 in close proximity to the diffusion region 132. The diffusion layer 135 is heavily doped n-type and is disposed adjacent to the reset gate 133. The diffusion layer 135 is biased by a DC voltage V_(r) that is at a higher level than the well potential in charge transfer region 76 f _(n). A pulsed voltage on the reset gate 133 causes the diffusion layer to be reset to the DC voltage V_(r).

The transient coupling region 300 includes a reset transistor 140 similar to reset transistor 137, a pseudo charge storage cell 28 x, and a gate 302. The reset transistor 140 includes a diffusion region 120 disposed in region 106 of the substrate 13, a reset gate 142 coupled to the control circuit 27, and a diffusion region 144 biased to DC voltage V_(r). Portions of transient signals travelling through the body 12 due to, e.g., edges of clocking signals such as a frame sync signal or a pixel clock signal discussed below, are coupled through the diffusion region 120. The diffusion region 120 is displaced from the diffusion region 132 far enough that the diffusion region 120 will not attract charges from the charge transfer region 128, but is disposed near enough to the diffusion region 132 such that the diffusion region 120 receives substantially the same transient signals as the diffusion region 132 does. The gate 302 is biased to voltage V_(d) and couples the region 106 to the pseudo charge storage cell 28 x. The pseudo charge storage cell 28 x, shown in simplified fashion, is configured the same as charge storage cells 28 ₁-28 _(n) except that it is isolated from other charge storage cells 28 and from the charge transfer devices 30. Thus, as shown, the BCCD layer 50 has an edge 304 disposed proximate to an edge 306 of the pseudo charge storage cell 28 x.

The transient suppression circuit 26 includes a main signal buffer amplifier 146 coupled to the input port 100, a pseudo signal buffer amplifier 162 coupled to the input port 102, and a differencing amplifier 150 for subtracting signals at the pair of input ports 100 and 102 to reduce transient signal components of the signal on input port 100. The main signal buffer amplifier 146 is coupled to the output port 32 and includes a main signal output port 122. The pseudo signal buffer amplifier is connected to a diffusion region 120 of the body 12 and provides a pseudo signal output port 124.

The main signal buffer amplifier 146 processes charges received from the output port 32. The diffusion region 132 of the reset transistor 137 serves as a floating diffusion charge detector. Detected charges are coupled through a line 134 to the output port 32 of the charge transfer device read-out electronics 18. Line 134 (FIGS. 1 and 2) couples charges from the output port 32 through the input port 100 to the main signal buffer amplifier 146, inducing a corresponding current signal at the main signal output port 122. Port 122 is coupled through a line 148 to the differencing amplifier 150. Alternatively, port 122 may be coupled, e.g., to one of the pins 15 (FIG. 1) on the periphery of the body 12.

The pseudo signal buffer amplifier 162 processes signals present in the body 12. Charges due to transient signals are coupled from the diffusion region 120, which serves as a transient signal sensor, by a line 152 (FIGS. 1 and 2) through the input port 102 to the pseudo signal buffer amplifier 162. The sensed transient signals on line 152 induce a corresponding sensor output current signal at the pseudo signal output port 124. Port 124 is coupled through a line 164 to the differencing amplifier 150. As with port 122, port 124 may be coupled, e.g., to one of the pins 15 (see FIG. 1) on the periphery of the body 12.

The differencing amplifier 150 is configured to remove the signal on line 164 (i.e., the output of amplifier 162) from the signal on line 148 (i.e., the output of amplifier 146). The output of the amplifier 146 is a boxcar signal as shown in FIG. 7B, having a DC bias of about +1V, having a period matching the period of the charge transfer device read-out electronics 18, and having heights of signal portions 165 representative of energy detected by the detectors 16 ₁-16 _(n) (i.e., the output of the amplifier 146 is an analog signal digitally controlled). This signal also includes transients from the system 10 that are not representative of energy detected by the detectors 16 ₁-16 _(n). The output of the amplifier 162 is also a boxcar signal that is representative of the transients in the system 10 but not of the energy detected by the detectors 16 ₁-16 _(n). Thus, by matching and subtracting the signal on line 164 from the signal on line 148, the differencing amplifier 150 performs common mode rejection, yielding a signal on line 166 (see also FIGS. 1 and 2) representative of detected energy and little, if any, stray energy. “Matching” means that the signals on lines 148 and 164 are amplified so that the transients present in both signals are substantially equal in magnitude. The signal on line 166 facilitates analog to digital conversion for, e.g., image processing.

Control Circuit

The control circuit 27 is shown in FIG. 8 to provide control signals to each of the read-out electronics driver sections 20, and to each of the charge coupling structure driver sections 24 (it being noted that, for clarity, only the read-out electronics driver section 20 and the charge coupling structure driver section 24 for quadrant 14 d are shown) to control energy detection and readout from the detectors 16 ₁-16 _(n). Clock bias signals CLCBIAS, a ground potential GND, and bias potentials V_(DD), V_(SS), VD_(low), VD_(high), HD_(low) and HD_(high) are supplied to the system 10 through the pins 15 (FIG. 1). Due to the doping profiles and configurations discussed above, VD_(high) and HD_(high) are +5V and VD_(low) and HD_(low) are −5V. A pixel clock signal 168 and a frame sync signal 170 are supplied to the system 10 through the pins 15 to the control circuit 27. The control circuit 27 processes the pixel clock and frame sync signals in on-chip multiphase clock generation circuitry to produce charge coupling structure clock signals (i.e., vertical clock signals) VC₁-VC₂ and charge transfer device read-out electronics clock signals (i.e., horizontal clock signals) HC₁ and HC₂.

The charge coupling structure driver section 24 processes the vertical clock signals VC₁-VC₂ to produce vertical driver signals VDS₁-VDS₂. These clock signals are square waves swinging between two bias voltages, VD_(high) and VD_(low), and are coupled to the charge transfer devices 30 ₁-30 _(n), (i.e., vertical CTDs) in parallel.

The read-out electronics driver section 20 processes the horizontal clock signals HC₁ and HC₂ to produce horizontal driver signals CDS₁ and HDS₂ for the charge transfer device read-out electronics 18 (i.e., the horizontal CTD 18). The horizontal driver signals HDS₁ and HDS₂ are square waves swinging between two bias voltages, HD_(high) and HD_(low), and are coupled to the gates, e.g., to gates 78 a ₁ -c ₁-78 a _(n) -c _(n) and 78 d ₁ -f ₁-78 d _(n) -f _(n), respectively (see FIG. 6), of the charge storage cells 28 ₁-28 _(n).

The control circuit 27 also regulates the charge detector 137. A pulsed voltage reset signal RST is sent from the control circuit 27 to the reset transistors 137 and 140 just before the read-out electronics begins serially transferring charges from the n charge storage cells 28 ₁-28 _(n).

The control circuit 27 is disposed at one end of the body 12 (FIG. 1). This isolates the control circuit 27 from the rest of the system 10 and enables the body to be configured such that the control circuit 27 can be separated from the rest of the system 10. For example, the control circuit 27 can be formed on a portion of the body 12 that can be easily detached and replaced, with the control circuit 27 coupled by bond wires to the rest of the system 10. Thus, if the control circuit 27 fails, it can be easily removed and replaced with a new control circuit that is then bond wired to the rest of the system 10.

Filters and Scanning Apparatus

As shown in FIG. 9, a filter subsystem 171 including a wavelength filter 172, a polarization separator 174 (e.g., a birefringent wedge), a shield 175, and a polarizer 176, are arranged to pass copolarized radiation to one row of detectors 16 a and crosspolarized radiation to another other row of detectors 16 b. The filter 172 is disposed above the body 12 to intercept radiation as indicated by rays R₁, R₂ and R₃, which have wavelengths λ₁, λ₂ and λ₃ respectively. The filter 172 inhibits radiation, e.g., ray R₃, having a wavelength outside a desired range from passing through the filter 172. Radiation, e.g., rays R₁ and R₂, having wavelengths within the desired range is allowed to pass through the filter 172 to the separator 174.

The separator 174 separates incident radiation into orthogonal polarizations, sending copolarized radiation R_(1co) of ray R₁ toward the first row of detectors 16 a and crosspolarized radiation R_(1x) of ray R₁ toward the second row of detectors 16 b. To separate the orthogonal polarizations of radiation, the separator 174 affects the phasing of the two polarizations differently. However, because the two rays R₁ and R₂ are incident from different areas, and therefore have different incident angles with respect to the separator 174, some of the crosspolarized radiation R_(2x) of ray R₂ is directed by the separator 174 toward the first row of detectors 16 a.

The shield 175 allows radiation, whether copolarized or crosspolarized, to impinge upon the rows of detectors 16 aand 16 b while inhibiting the radiation from impinging upon other portions of the system 10. Radiation is permitted to pass through openings 177 and 179 in the shield 175 to the polarizer 176. The openings 177 and 179 have sizes substantially matched to sizes of the arrays 17.

The polarizer 176 helps ensure that only copolarized radiation reaches the first row of detectors 16 a and only crosspolarized radiation reaches the second row of detectors 16 b, which are separated by an insulator 178. Portions 176 a and 176 b only allow copolarized and crosspolarized radiation, respectively, to pass through them. Therefore, the crosspolarized radiation R_(2x) is not allowed to reach detectors 14 a.

As shown in FIG. 10, the detection system 10 may be scanned using a gimbal arrangement 180. The gimbal arrangement 180 includes a motor/base 182, a bottom member 184 and a top member 186 attached to the bottom of system 10. The motor 182 cyclically drives the top member 186 to pivot with respect to the bottom member 184 about a pin 188, causing a field of view of the detectors 16 to be scanned as indicated by arc 190. Thus, the field of view of the detectors 16 is directed at different portions of the arc 190 at different times during a cycle of the motor 182.

Operation

In operation, electromagnetic energy is impinged upon the system 10 by directing the system 10, and filtering and separating the impinging energy, as desired using, e.g., the apparatus of FIGS. 9-10. For example, laser energy is directed at a target and the system 10 is directed to receive the laser energy reflected from the target. More particularly, the system 10 can detect YAG laser radiation if PtSi detectors are used for the detectors 16.

By controlling the timing and amplitudes of the vertical driver signals VDS₁-VDS₂ and the horizontal driver signals HDS₁-HDS₂, the control circuit 27 regulates the transfer of charge from the detectors 16 ₁-16 _(n) in each of the quadrants 14 a-d to the output port 32. Beginning at the first rising edge of the pixel clock signal 168 after the frame sync signal 170 changes to its active state, the control circuit 27 sequentially actuates gates 56 ₁-56 _(n) in parallel and 60 ₁-60 _(n) (see FIG. 3) in parallel. Potential wells are sequentially produced similar to those shown in FIGS. 5B and 5C to transfer charge produced in the detectors 16 ₁-16 _(n) to charge transfer regions 74 ₁-74 _(n) where the charges are then ready to be transferred to the charge storage cells 28 ₁-28 _(n) of the charge transfer device read-out electronics 18. Gate 210 (FIG. 5A) is then activated while HDS₁ and HDS₂ are set to fixed levels, thus allowing charge to flow into the charge storage cells 28 ₁-28 _(n). Gate 210 is then deactivated. The control circuit 27 then actuates the gates 78 a ₁ -f ₁-78 a ₁ -f _(n) to produce potential gradients, similar to those shown in FIGS. 5B and 5C, to serially move the charges to the output port 32.

It is noted that charges produced in the detectors 16 ₁-16 _(n) are inhibited from passing through any diffusion regions or ohmic contacts between the detectors 16 ₁-16 _(n) and the end of the charge transfer device read-out electronics 18. The charges produced in the detectors 16 ₁-16 _(n) are transferred within (i.e., remain in) the substrate 13 until read out through the diffusion region 132 to the output port 32. This helps reduce noise and improve SNR, helping detection of near-infrared radiation that is substantially transparent to the substrate 13.

While the charges from the detectors 16 ₁-16 _(n) are integrated and transferred in parallel through the charge transfer devices 30 ₁-30 _(n) to the charge storage cells 28 ₁-28 ₁ of the charge transfer device read-out electronics 18, earlier-produced charges are serially transferred to, and read out from, the output port 32.

As the charges are received by the output port 32, signals are induced in the main signal circuit 116 and the pseudo signal circuit 118. These induced signals are amplified in buffer amplifiers 146 and 162. The amplified signals are coupled to the differencing amplifier 150 which rejects common modes of the outputs of the buffer amplifiers 146 and 162, yielding a signal that is substantially free of information unrelated to the detected energy from the detectors 16 ₁-16 _(n). Alternatively, the amplified signals can be coupled to pins 15 for processing external to the system 10.

Other embodiments are within the spirit and scope of the appended claims. For example, instead of using the gimbal arrangement of FIG. 10, as shown in FIG. 11 the system 10 could be scanned using a moving window 192 having an aperture 194. The aperture 194 permits energy within a field of view 196 to reach the row of detectors 16 a. By moving the window 192, the field of view 196 shifts, thereby exposing the detectors 16 to energy from different areas. Alternatively, the window 192 could be configured to be stationary, with the aperture 194 moving within the window 192. Also, the system 10 can include appropriate internal clock generators to produce the frame sync signal 170 and the pixel clock signal 168. Thus, these signals do not need to be brought in from outside of the system 10 through the pins 15.

Furthermore, a Brewer detector can be coupled to the end of the charge transfer device read-out electronics 18 to eliminate the diffusion region 132 (FIG. 7A). A Brewer detector arrangement 400 is shown schematically in FIG. 12. A PMOS transistor 402 has its drain 404 coupled to the substrate 13 in the output port region 104. The drain 404 is further coupled to a gate 406 of the transistor 402 and biased to a fixed DC voltage V_(bias1). A source 408 of the transistor 402 is coupled through line 410 to a buffer amplifier 412. The line 410 is also coupled to a fixed DC voltage V_(bias2) (e.g., +5V) through a current source I_(bias). The presence of a buried channel charge packet 414 is detected as a difference in the voltage at the source 408. The buffer amplifier 412 provides the main signal output port 122 (FIG. 7A). For more information about Brewer detectors, reference is made to “The Low Light Level Potential of a CCD Imaging Array” by R. J. Brewer, IEEE Transactions on Electron Devices, Vol. ED-27, No. 2, February, 1980. 

What is claimed is:
 1. A detection system, comprising: a single crystal body having a plurality of doped regions disposed therein; an array of detectors arranged in at least one row and a plurality of columns, each one of the detectors producing charge in a corresponding one of the doped regions in the body in response to electromagnetic energy impinging upon such one of the detectors; a first charge transfer device including an output port and a plurality of serially coupled charge storage cells, such device including a plurality of first charge transfer regions disposed in the body parallel to the at least one row of detectors; a plurality of second charge transfer devices, each including a second charge transfer region disposed in the body, each one of the plurality of second charge transfer devices being disposed transverse to the at least one row of detectors and the first charge transfer device, each one of the plurality of second charge transfer regions being adapted to transfer charge produced in a corresponding one of the doped regions to a corresponding one of the plurality of charge storage cells; a controller coupled to the first charge transfer device and the plurality of second charge transfer devices, the controller adapted to regulate the transfer of charge from the doped regions corresponding to the detectors to the output port; and wherein each one of the doped regions corresponding to one of the detectors has a doping profile adapted to produce an electric field in a direction from the doped region toward a corresponding one of the plurality of second charge transfer regions.
 2. The system recited in claim 1 wherein the charge portion of each of the detectors includes a plurality of doped regions whose doping concentrations vary monotonically from one end of the charge portion to the other end.
 3. The system recited in claim 2 wherein each of the charge portions provides a monotonically varying voltage at a predetermined depth of each charge portion.
 4. The system recited in claim 1 wherein the charge portion of each detector extends across a majority of a width of the detector.
 5. In combination: a single crystal body; a detector having a doped region disposed in a surface of the body, such detector being adapted to produce charge in the doped region in response to electromagnetic energy impinging upon such detector through the surface of the body; a second region disposed in the body and displaced from the detector along a direction parallel to the surface of the body; and wherein the doped region has a doping profile selected to produce an electric field therein in along the direction parallel to the body to urge the charge produced in the doped region of the detector towards the second region.
 6. The combination recited in claim 5 wherein the single crystal body comprises silicon.
 7. The combination recited in claim 5 wherein the detector comprises a light detector.
 8. The combination recited in claim 5 further comprising a buried channel charge coupled device disposed in the second region.
 9. The combination recited in claim 5 wherein the region of the detector includes a plurality of regions having different doping concentrations selected together to vary monotonically in the direction toward the second.
 10. An electromagnetic energy detection system comprising: a single crystal body; a detector, disposed in a first region of the body, for producing charge in the body in response to electromagnetic energy impinging upon such detector, and for providing at least a portion of the produced charge through a second region of the body to an output port; a charge detector coupled to the output port and producing a charge detector output signal indicative of detected charges; and a sensor having an input port coupled to the body in a third region of the body and producing a sensor output signal indicative of signals induced on the input port.
 11. The system recited in claim 10 further comprising a differencing device coupled to the charge detector and the sensor, the differencing device adapted to produce a differencing device output indicative of a comparison of the sensor output signal and the charge detector output signal.
 12. The system recited in claim in claim 10 wherein the detection system is further adapted to transfer charge form the first region through a third region of the body to the output port, the second region being disposed sufficiently far from the third region to attract substantially no charges from the third region and sufficiently close to the third region to receive substantially the same transient signals as received by the third region.
 13. In a system including a charge transfer device formed in a first region of a single crystal body, an apparatus comprising: a first input coupled to an output of the charge transfer device; a second input coupled to a second region of the body displaced from the first region; and a differencing arrangement coupled to the first and second inputs and adapted to subtract a second signal present at the second input from a first signal present at the first input. 